The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A FET, such as FET 10 illustrated in FIG. 1, includes a gate electrode 12 as a control electrode overlying a gate insulator 32 that is disposed on a semiconductor substrate 14. Spaced-apart source and drain electrodes 16 between which a current can flow also are disposed in the substrate. The source and drain electrodes 16 typically are formed using two steps. First, conductivity-determining ions are implanted into the substrate 14 using the gate electrode 12 as an ion implantation mask to form shallow impurity doped regions or source and drain extensions. Same or different conductivity-determining ions then are implanted into the substrate 14 at a higher energy using the gate electrode 12 and sidewall spacers 28 disposed adjacent to sidewalls 34 of the gate electrode as an ion implantation mask. Metal silicide 20 is formed on the gate electrode 12 and the source and drain electrodes 16 to make electrical contact thereto. An interlayer dielectric (ILD) 22 is typically deposited over the gate electrode and source and drain electrodes and a conductive contact 24 is formed within the ILD to contact the source and/or drain electrodes. A control voltage applied to the gate electrode controls the flow of current through a channel 18 in the substrate between the source and drain electrodes 16.
The gate electrode 12 is formed of a conductive material, typically polycrystalline silicon. The height, indicated by double-headed arrow 26, of the gate electrode 12 is determined by several factors. The gate electrode 12 should have a height 26 sufficiently large to prevent conductivity-determining ions from penetrating through the gate electrode into the channel 18 of the substrate during formation of the source and drain regions. The gate electrode also should have a height 26 sufficiently large so that sidewall spacers 28 are formed consistent in width and wide enough to separate the gate electrode 12 from the metal silicide contacts 20 on the source and drain regions.
Another factor determining the height of the gate electrode is the desired width of the gate electrode. MOS transistors have now been aggressively reduced to the point at which the gate electrode of the transistor is less than or equal to 40 nanometers (nm) in width. One of the limiting factors in the continued shrinking of integrated semiconductor devices is the difficulty in obtaining high aspect ratio gate electrode definitions, that is, very high and very narrow gate electrodes. To form such structures, relatively thin layers of resist are used during photolithography. However, during patterning of the gate electrode using reactive ion etching (RIE), the thin resist can be etched away, resulting in etching of the gate electrode. Accordingly, the gate electrode should have a height 26 small enough that formation of the gate electrode using current photolithography technologies is possible. Thus, present day technology generally requires a gate electrode having a thickness in the range of about 80 to about 150 nm.
Another challenge in the fabrication of FETs resulting from the gate electrode geometry is the creation of parasitic capacitance, shown for the purposes of illustration as dashed lines 30, between the gate electrode 12 and the proximate contact 24. The parasitic capacitance 30 is proportional to the area of the interfacing structures, that is, the gate electrode 12 and the contact 24. Accordingly, the greater the height 26 of the gate electrode, the greater the parasitic capacitance.
A major challenge relating to the gate electrode geometry is the localized penetration of silicide 20 from the top of the gate electrode 12 towards the gate oxide 32, as illustrated in FIG. 2. This phenomenon, referred to as “silicide roughness”, is thought to be associated with portions of the polycrystalline silicon sidewalls 34 of the gate electrode, which become exposed due to non-uniform sidewall spacer 28 recess during various etch and cleaning processes. The roughness results in non-reproducible resistivity characteristics from device to device. In addition, if the silicide penetration extends the entire sidewall 34 of the gate electrode 12 to the gate insulator 32, catastrophic device failure will result from a short circuit between the gate electrode 12 to the source and drain electrodes.
Accordingly, it is desirable to provide a field effect transistor that experiences reduced parasitic capacitance during operation. In addition, it is desirable to provide a field effect transistor that does not suffer from silicide roughness. It also is desirable to provide methods for forming such field effect transistors. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.